module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
	
	localparam IDLE =2'b00;
	localparam S1=2'b01;
	localparam S2=2'b11;
	localparam S3=2'b10;
	reg [1:0]state;
	reg [1:0]next_state;
	always@(posedge clk or negedge aresetn)begin
		if(!aresetn)begin
			state<=IDLE;
		end
		else begin
			state<=next_state;
		end
	end
	
	always@(*)begin
		case(state)
			IDLE:begin
				next_state=(x)?S1:IDLE;//***
				z=1'b0;
			end
			S1:begin
				next_state=(x)?S1:S2;//1*
				z=1'b0;
			end
			S2:begin//10*
				next_state=(x)?S3:IDLE;
				z=(x)?1'b1:1'b0;
			end
			S3:begin//101*
				next_state=(x)?S1:S2;
				z=1'b0;
			end
		endcase
	end
	
endmodule